1. Field of the Invention
This invention relates to a memory device with an ECC system installed therein.
2. Description of the Related Art
In a memory device with a large capacity scale such as a NAND-type flash memory, a resistance change memory (ReRAM) and a phase change memory (PCRAM) and the like, data contents are destroyed during data holding due to variable causes. Specifically, in case the physical mechanism used for holding a data state is easily affected by noise, and when the large scale integration of the memory capacity and the size-shrinking in the fabricating process progress more, the error rate of the memory device will be increased more. Therefore, it becomes a key technology to install an on-chip ECC (Error Correcting Code) system in a memory device.
There has already been provided such a technology that an ECC circuit is installed in a flash memory chip or a memory controller thereof (refer to, for example, JP-A-2000-173289).
In case error correction is performed for two bits or more in an ECC system with BCH code (i.e., BCH-ECC system) using Galois finite field GF(2n), if such a method is used that the finite field elements are substituted sequentially for solving an error location searching equation, the operation time becomes very long, so that the read and write performance of the memory will be declined largely even if the ECC system is installed therein.
So, it is desired to install an ECC system, which does not use the above-described sequential substitution method and does not sacrifice the memory performance.